// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2023 Andes Technology Corporation
 */

#ifndef _ASM_DCF_CSR_H
#define _ASM_DCF_CSR_H

#define CSR_DCF_MCCTL	 0x7ca
#define CSR_DCF_MCCTLCMD 0x7cc
#define CSR_DCF_MMISCCTL 0x7d0
#define CSR_DCF_MIMCFG   0xfc0
#define CSR_DCF_MDMCFG   0xfc1
#define CSR_DCF_MHINTCFG 0xfc2

/* MMSC configuration register */
#define V5_MMSC_CFG_TLB_ECC_OFFSET_1			1
#define V5_MMSC_CFG_TLB_ECC_OFFSET_2			2

#define V5_MMSC_CFG_TLB_ECC_1					BIT(V5_MMSC_CFG_TLB_ECC_OFFSET_1)
#define V5_MMSC_CFG_TLB_ECC_2					BIT(V5_MMSC_CFG_TLB_ECC_OFFSET_2)

/* MICM configuration regiser */
#define V5_MIMCFG_IC_ECC_OFFSET_1				10
#define V5_MIMCFG_IC_ECC_OFFSET_2				11

#define V5_MIMCFG_IC_ECC_1					BIT(V5_MIMCFG_IC_ECC_OFFSET_1)
#define V5_MIMCFG_IC_ECC_2					BIT(V5_MIMCFG_IC_ECC_OFFSET_2)

/* MDCM configuration regiser */
#define V5_MDMCFG_DC_ECC_OFFSET_1				10
#define V5_MDMCFG_DC_ECC_OFFSET_2				11

#define V5_MDMCFG_DC_ECC_1					BIT(V5_MDMCFG_DC_ECC_OFFSET_1)
#define V5_MDMCFG_DC_ECC_2					BIT(V5_MDMCFG_DC_ECC_OFFSET_2)

/* MMISC control register */
#define DCF_MMISCCTL_NON_BLOCKING_OFFSET		8
#define DCF_MMISCCTL_NON_BLOCKING_EN			BIT(DCF_MMISCCTL_NON_BLOCKING_OFFSET)

/* MCACHE control register */
#define DCF_MCCTL_IC_EN_OFFSET				0
#define DCF_MCCTL_DC_EN_OFFSET				1
#define DCF_MCCTL_IC_ECCEN_OFFSET_1			2
#define DCF_MCCTL_IC_ECCEN_OFFSET_2			3
#define DCF_MCCTL_DC_ECCEN_OFFSET_1			4
#define DCF_MCCTL_DC_ECCEN_OFFSET_2			5
#define DCF_MCCTL_CCTL_SUEN_OFFSET			8
#define DCF_MCCTL_L1I_PREFETCH_OFFSET		9
#define DCF_MCCTL_L1D_PREFETCH_OFFSET		10
#define DCF_MCCTL_DC_WMERGE_OFFSET_1		13
#define DCF_MCCTL_DC_WMERGE_OFFSET_2		14
#define DCF_MCCTL_L2C_WMERGE_OFFSET_1		15
#define DCF_MCCTL_L2C_WMERGE_OFFSET_2		16
#define DCF_MCCTL_TLB_ECCEN_OFFSET_1		17
#define DCF_MCCTL_TLB_ECCEN_OFFSET_2		18
#define DCF_MCCTL_DC_COHEN_OFFSET			19
#define DCF_MCCTL_DC_COHSTA_OFFSET			20

#define DCF_MCCTL_IC_EN						BIT(DCF_MCCTL_IC_EN_OFFSET)
#define DCF_MCCTL_DC_EN						BIT(DCF_MCCTL_DC_EN_OFFSET)
#define DCF_MCCTL_IC_ECCEN_1				BIT(DCF_MCCTL_IC_ECCEN_OFFSET_1)
#define DCF_MCCTL_IC_ECCEN_2				BIT(DCF_MCCTL_IC_ECCEN_OFFSET_2)
#define DCF_MCCTL_DC_ECCEN_1				BIT(DCF_MCCTL_DC_ECCEN_OFFSET_1)
#define DCF_MCCTL_DC_ECCEN_2				BIT(DCF_MCCTL_DC_ECCEN_OFFSET_2)
#define DCF_MCCTL_CCTL_SUEN					BIT(DCF_MCCTL_CCTL_SUEN_OFFSET)
#define DCF_MCCTL_L1I_PREFETCH_EN			BIT(DCF_MCCTL_L1I_PREFETCH_OFFSET)
#define DCF_MCCTL_L1D_PREFETCH_EN			BIT(DCF_MCCTL_L1D_PREFETCH_OFFSET)
#define DCF_MCCTL_DC_WMERGE_1_EN			BIT(DCF_MCCTL_DC_WMERGE_OFFSET_1)
#define DCF_MCCTL_DC_WMERGE_2_EN			BIT(DCF_MCCTL_DC_WMERGE_OFFSET_2)
#define DCF_MCCTL_L2C_WMERGE_1_EN			BIT(DCF_MCCTL_L2C_WMERGE_OFFSET_1)
#define DCF_MCCTL_L2C_WMERGE_2_EN			BIT(DCF_MCCTL_L2C_WMERGE_OFFSET_2)
#define DCF_MCCTL_TLB_ECCEN_1				BIT(DCF_MCCTL_TLB_ECCEN_OFFSET_1)
#define DCF_MCCTL_TLB_ECCEN_2				BIT(DCF_MCCTL_TLB_ECCEN_OFFSET_2)
#define DCF_MCCTL_DC_COHEN_EN				BIT(DCF_MCCTL_DC_COHEN_OFFSET)
#define DCF_MCCTL_DC_COHSTA_EN				BIT(DCF_MCCTL_DC_COHSTA_OFFSET)

/* CCTL command */
#define CCTL_L1D_WBINVAL_ALL    6

#endif /* _ASM_DCF_CSR_H */
